Pixel array including air gap reflection structures

ABSTRACT

A pixel array may include air gap reflection structures under a photodiode of a pixel sensor to reflect photons that would otherwise partially refract or scatter through a bottom surface of a photodiode. The air gap reflection structures may reflect photons upward toward the photodiode so that the photons may be absorbed by the photodiode. This may increase the quantity of photons absorbed by the photodiode, which may increase the quantum efficiency of the pixel sensor and the pixel array.

RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.16/949,927, filed Nov. 20, 2020, which is incorporated herein byreference in its entirety.

BACKGROUND

Digital cameras and other optical imaging devices employ image sensors.Image sensors convert optical images to digital data that may berepresented as digital images. An image sensor includes an array ofpixel sensors and supporting logic. The pixel sensors of the array areunit devices for measuring incident light, and the supporting logicfacilitates readout of the measurements. One type of image sensorcommonly used in optical imaging devices is a back side illumination(BSI) image sensor. BSI image sensor fabrication can be integrated intosemiconductor processes for low cost, small size, and high integration.Further, BSI image sensors may have low operating voltage, low powerconsumption, high quantum efficiency, low read-out noise, and may allowrandom access.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a diagram of an example environment in which systems and/ormethods described herein may be implemented.

FIG. 2 is a diagram of an example pixel array described herein.

FIG. 3 is a diagram of example image sensor described herein.

FIGS. 4A-4S are diagrams of an example implementation described herein.

FIGS. 5-7 are diagrams of example image sensors described herein.

FIG. 8 is a diagram of example air gap reflection structureconfigurations described herein.

FIG. 9 is a diagram of example components of one or more devices of FIG.1 .

FIG. 10 is a flowchart of an example process relating to forming animage sensor described herein.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper,” “over,” “under,” and the like, may be used herein forease of description to describe one element or feature's relationship toanother element(s) or feature(s) as illustrated in the figures. Thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. The apparatus may be otherwiseoriented (rotated 90 degrees or at other orientations) and the spatiallyrelative descriptors used herein may likewise be interpretedaccordingly.

Some techniques may be used to increase the quantum efficiency of apixel sensor. The quantum efficiency of a pixel sensor may be determinedas a ratio of the number of photons of incident light collected by thepixel to the number of total photons of incident light directed towardthe pixel sensor. One example technique includes forming isolationstructures on each side of the photodiode associated with the pixelsensor to reduce optical crosstalk between adjacent pixel sensors. Theisolation structures may reduce or prevent photons from diffusing intoadjacent photodiodes. However, some photons may still at least partiallyrefract, diffuse, or scatter through a bottom surface of a photodiode ina pixel sensor to the layers beneath the pixel sensor, which can causereduce the quantum efficiency of the pixel sensor.

Some implementations described herein provide techniques and apparatusesfor a pixel array that includes air gap reflection structures under aphotodiode of a pixel sensor to reflect photons that would otherwisepartially refract, diffuse, or scatter through a bottom surface of aphotodiode. In this way, the air gap reflection structures reflectphotons upward toward the photodiode so that the photons may be absorbedby the photodiode. This may increase the quantity of photons absorbed bythe photodiode, which may increase the quantum efficiency of the pixelsensor and the pixel array and/or may decrease the resistive-capacitive(RC) delay of the pixel sensor.

The air gap reflection structures may include holes or trenches formedin one or more layers below the photodiode. A material (e.g., adielectric material) may be deposited over the openings of the air gapreflection structures to seal the air gap reflection structures suchthat the air gap reflection structures are primarily filled with air.Air has the lowest refractive index of all materials and is the closestto the refractive index of a vacuum. The low refractive index of airrelative to the refractive index of the material (e.g., silicon) of thesubstrate layer in which the photodiode is formed lowers the criticalangle for a total internal reflection at the boundary between thesubstrate layer material and the air gaps. Photons traveling through thephotodiode toward the boundary between the substrate layer material andthe air gap at an angle that is equal to or greater than the criticalangle may totally reflect off of the substrate layer material-air gapboundary, which causes the photons to be redirected toward and to remainin the photodiode. Thus, the lower critical angle increases thelikelihood that a total internal reflection of incident light will occurin the photodiode, which further increases the quantum efficiency of thepixel sensor and the pixel array.

FIG. 1 is a diagram of an example environment 100 in which systemsand/or methods described herein may be implemented. As shown in FIG. 1 ,environment 100 may include a plurality of semiconductor processingtools 102-114 and a wafer/die transport tool 116. The plurality ofsemiconductor processing tools 102-114 may include a deposition tool102, an exposure tool 104, a developer tool 106, an etch tool 108, aplanarization tool 110, a plating tool 112, an ion implantation tool114, and/or another type of semiconductor processing tool. The toolsincluded in example environment 100 may be included in a semiconductorclean room, a semiconductor foundry, a semiconductor processing and/ormanufacturing facility, and/or the like.

The deposition tool 102 is a semiconductor processing tool that includesa semiconductor processing chamber and one or more devices capable ofdepositing various types of materials onto a substrate. In someimplementations, the deposition tool 102 includes a spin coating toolthat is capable of depositing a photoresist layer on a substrate such asa wafer. In some implementations, the deposition tool 102 includes achemical vapor deposition (CVD) tool such as a plasma-enhanced CVD(PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, asub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool,a plasma-enhanced atomic layer deposition (PEALD) tool, or another typeof CVD tool. In some implementations, the deposition tool 102 includes aphysical vapor deposition (PVD) tool, such as a sputtering tool oranother type of PVD tool. In some implementations, the exampleenvironment 100 includes a plurality of types of deposition tools 102.

The exposure tool 104 is a semiconductor processing tool that is capableof exposing a photoresist layer to a radiation source, such as anultraviolet light (UV) source (e.g., a deep UV light source, an extremeUV light (EUV) source, and/or the like), an x-ray source, an electronbeam (e-beam) source, and/or the like. The exposure tool 104 may exposea photoresist layer to the radiation source to transfer a pattern from aphotomask to the photoresist layer. The pattern may include one or moresemiconductor device layer patterns for forming one or moresemiconductor devices, may include a pattern for forming one or morestructures of a semiconductor device, may include a pattern for etchingvarious portions of a semiconductor device, and/or the like. In someimplementations, the exposure tool 104 includes a scanner, a stepper, ora similar type of exposure tool.

The developer tool 106 is a semiconductor processing tool that iscapable of developing a photoresist layer that has been exposed to aradiation source to develop a pattern transferred to the photoresistlayer from the exposure tool 104. In some implementations, the developertool 106 develops a pattern by removing unexposed portions of aphotoresist layer. In some implementations, the developer tool 106develops a pattern by removing exposed portions of a photoresist layer.In some implementations, the developer tool 106 develops a pattern bydissolving exposed or unexposed portions of a photoresist layer throughthe use of a chemical developer.

The etch tool 108 is a semiconductor processing tool that is capable ofetching various types of materials of a substrate, wafer, orsemiconductor device. For example, the etch tool 108 may include a wetetch tool, a dry etch tool, and/or the like. In some implementations,the etch tool 108 includes a chamber that is filled with an etchant, andthe substrate is placed in the chamber for a particular time period toremove particular amounts of one or more portions of the substrate. Insome implementations, the etch tool 108 may etch one or more portions ofthe substrate using a plasma etch or a plasma-assisted etch, which mayinvolve using an ionized gas to isotopically or directionally etch theone or more portions.

The planarization tool 110 is a semiconductor processing tool that iscapable of polishing or planarizing various layers of a wafer orsemiconductor device. For example, a planarization tool 110 may includea chemical mechanical planarization (CMP) tool and/or another type ofplanarization tool that polishes or planarizes a layer or surface ofdeposited or plated material. The planarization tool 110 may polish orplanarize a surface of a semiconductor device with a combination ofchemical and mechanical forces (e.g., chemical etching and free abrasivepolishing). The planarization tool 110 may utilize an abrasive andcorrosive chemical slurry in conjunction with a polishing pad andretaining ring (e.g., typically of a greater diameter than thesemiconductor device). The polishing pad and the semiconductor devicemay be pressed together by a dynamic polishing head and held in place bythe retaining ring. The dynamic polishing head may rotate with differentaxes of rotation to remove material and even out any irregulartopography of the semiconductor device, making the semiconductor deviceflat or planar.

The plating tool 112 is a semiconductor processing tool that is capableof plating a substrate (e.g., a wafer, a semiconductor device, and/orthe like) or a portion thereof with one or more metals. For example, theplating tool 112 may include a copper electroplating device, an aluminumelectroplating device, a nickel electroplating device, a tinelectroplating device, a compound material or alloy (e.g., tin-silver,tin-lead, and/or the like) electroplating device, and/or anelectroplating device for one or more other types of conductivematerials, metals, and/or similar types of materials.

The ion implantation tool 114 is a semiconductor processing tool that iscapable of implanting ions into a substrate. The ion implantation tool114 may generate ions in an arc chamber from a source material such as agas or a solid. The source material may be provided into the arcchamber, and an arc voltage is discharged between a cathode and anelectrode to produce a plasma containing ions of the source material.One or more extraction electrodes may be used to extract the ions fromthe plasma in the arc chamber and accelerate the ions to form an ionbeam. The ion beam may be directed toward the substrate such that theions are implanted below the surface of the substrate.

Wafer/die transport tool 116 includes a mobile robot, a robot arm, atram or rail car, and/or another type of device that is used totransport wafers and/or dies between semiconductor processing tools102-114 and/or to and from other locations such as a wafer rack, astorage room, and/or the like. In some implementations, wafer/dietransport tool 116 may be a programmed device that is configured totravel a particular path and/or may operate semi-autonomously orautonomously.

The number and arrangement of devices shown in FIG. 1 are provided asone or more examples. In practice, there may be additional devices,fewer devices, different devices, or differently arranged devices thanthose shown in FIG. 1 . Furthermore, two or more devices shown in FIG. 1may be implemented within a single device, or a single device shown inFIG. 1 may be implemented as multiple, distributed devices.Additionally, or alternatively, a set of devices (e.g., one or moredevices) of environment 100 may perform one or more functions describedas being performed by another set of devices of environment 100.

FIG. 2 is a diagram of an example pixel array 200 (or a portion thereof)described herein. The pixel array 200 may be included in an imagesensor, such as a complementary metal oxide semiconductor (CMOS) imagesensor, a back side illuminated (BSI) CMOS image sensor, or another typeof image sensor.

FIG. 2 shows a top-down view of the pixel array 200. As shown in FIG. 2, the pixel array 200 may include a plurality of pixel sensors 202. Asfurther shown in FIG. 2 , the pixel sensors 202 may be arranged in agrid. In some implementations, the pixel sensors 202 are square-shaped(as shown in the example in FIG. 2 ). In some implementations, the pixelsensors 202 include other shapes such as circle shapes, octagon shapes,diamond shapes, and/or other shapes.

The pixel sensors 202 may be configured to sense and/or accumulateincident light (e.g., light directed toward the pixel array 200). Forexample, a pixel sensor 202 may absorb and accumulate photons of theincident light in a photodiode. The accumulation of photons in thephotodiode may generate a charge representing the intensity orbrightness of the incident light (e.g., a greater amount of charge maycorrespond to a greater intensity or brightness, and a lower amount ofcharge may correspond to a lower intensity or brightness).

The pixel array 200 may be electrically connected to a back-end-of-line(BEOL) metallization stack (not shown) of the image sensor. The BEOLmetallization stack may electrically connect the pixel array 200 tocontrol circuitry that may be used to measure the accumulation ofincident light in the pixel sensors 202 and convert the measurements toan electrical signal.

As indicated above, FIG. 2 is provided as an example. Other examples maydiffer from what is described with regard to FIG. 2 .

FIG. 3 is a diagram of an example image sensor 300 (or a portionthereof) described herein. As shown in FIG. 3 , the image sensor 300 mayinclude the pixel array 200. FIG. 3 illustrates a cross-sectional viewof the image sensor 300, which includes a cross-sectional view of thepixel array 200 along line AA of FIG. 2 . The image sensor 300 mayinclude a CMOS image sensor, a BSI CMOS image sensor, or another type ofimage sensor. The image sensor 300 may be configured to be deployed invarious implementations, such as digital cameras, video recorders,night-vision cameras, automotive sensors and cameras, and/or other typesof light-sensing implementations.

As shown in FIG. 3 , the image sensor 300 may include a plurality ofregions, such as the pixel array 200, a metal shield region 302, abonding pad region 304 (which may also be referred to as an E-padregion), and a scribe line region 306. The pixel array 200 may includethe pixel sensors 202 of the image sensor 300, such as pixel sensor 202a and pixel sensor 202 b. In some implementations, the image sensor 300includes a greater quantity of pixel sensors 202 or fewer pixel sensors202 than the quantity of pixel sensors illustrated in FIG. 3 .

The metal shield region 302 may include one or more devices that aremaintained in an optically dark environment. For example, the metalshield region 302 may include a reference pixel that is used toestablish a baseline of an intensity of light for the image sensor 300.In some implementations, the metal shield region 302 includes peripherydevices, such as one or more application-specific integrated circuit(ASIC) devices, one or more system-on-chip (SOC) devices, one or moretransistors, and/or one or more other components configured to measurethe amount of charge stored by the pixel sensors 202 to determine lightintensity of incident light and/or to generate images and/or video(e.g., digital images, digital video).

The bonding pad region 304 may include one or more conductive bondingpads (or e-pads) and/or metallization layers through which electricalconnections between the image sensor 300 and outside devices and/orexternal packaging may be established. The scribe line region 306 mayinclude a region that separates one semiconductor die or portion of asemiconductor die that includes the image sensor 300 from an adjacentsemiconductor die or portion of the semiconductor die that includesother image sensors and/or other integrated circuits.

As further shown in FIG. 3 , the image sensor 300 may include variouslayers and/or structures. In some implementations, the image sensor 300may be mounted and/or fabricated on a carrier substrate (not shown)during one or more semiconductor processing operations to form the imagesensor 300. As shown in FIG. 3 , the image sensor 300 may include abuffer layer 310. The buffer layer 310 may include a dielectric materialsuch as a silicon oxide (SiO_(x)), a silicon nitride (Si_(x)N_(y)), asilicon oxynitride (SiON), tetraethyl orthosilicate oxide,phosphosilicate glass (PSG), borophosphosilicate glass (BPSG),fluorinated silica glass (FSG), carbon doped silicon oxide, or anotherdielectric material. The buffer layer 310 may serve as a layer by whichthe image sensor 300 is bonded to the carrier substrate so that backside processing may be performed on the image sensor 300.

As further shown in FIG. 3 , the image sensor 300 may include aninter-metal dielectric (IMD) layer 312 above and/or on the buffer layer310. The IMD layer 312 may include one or more layers of dielectricmaterial (e.g., a silicon oxide (SiO_(x)), a silicon nitride(Si_(x)N_(y)), a silicon oxynitride (SiON), tetraethyl orthosilicateoxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG),fluorinated silica glass (FSG), carbon doped silicon oxide, or anotherdielectric material). Various metallization layers 314 may be formed inand/or in between the layers of the IMD layer 312. The metallizationlayers 314 may include bonding pads, conductive lines, and/or othertypes of conductive structures that electrically connect the variousregions of the image sensor 300 and/or electrically connect the variousregions of the image sensor 300 to one or more external devices and/orexternal packaging. The metallization layers 314 may be interconnectedby contacts 316, which may also be referred to as vias. For example, ametallization layer 314 a may be electrically connected to ametallization layer 314 b by one or more contacts 316, the metallizationlayer 314 b may be electrically connected to a metallization layer 314 cby one or more contacts 316, the metallization layer 314 c may beelectrically connected to a metallization layer 314 d by one or morecontacts 316, and so on. The metallization layers 314 and the contacts316 may be referred to as a BEOL metallization stack, and may include aconductive material, such as gold, copper, silver, cobalt, tungsten, ametal alloy, or a combination thereof, among other examples.

As further shown in FIG. 3 , the image sensor 300 may include anun-doped silicate glass (USG) layer 318 above and/or on the IMD layer312. The USG layer 318 may function as an insulator and a passivationlayer between the IMD layer 312 and an interlayer dielectric (ILD) layer320 above the IMD layer 312. The ILD layer 320 may include a dielectricmaterial (e.g., a silicon oxide (SiO_(x)), a silicon nitride(Si_(x)N_(y)), a silicon oxynitride (SiON), tetraethyl orthosilicateoxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG),fluorinated silica glass (FSG), carbon doped silicon oxide, or anotherdielectric material).

As further shown in FIG. 3 , one or more air gap reflection structures322 may be formed and/or located through the USG layer 318 and at leastpartially in and/or through the ILD layer 320. The air gap reflectionstructures 322 may be configured to reflect photons of incident lightthat would otherwise refract, diffuse, and/or scatter through to the ILDlayer 320, the USG layer 318, and/or the IMD layer 312. One or more ofthe pixel sensors 202 may include one or more air gap reflectionstructures 322. For example, the pixel sensor 202 a may include one ormore air gap reflection structures 322 a, the pixel sensor 202 b mayinclude one or more air gap reflection structures 322 b, and so on. Insome implementations, all of the pixel sensors 202 in the pixel array200 include air gap reflection structures 322. In some implementations,a subset of the pixel sensors 202 in the pixel array 200 include air gapreflection structures 322.

An air gap reflection structure 322 may include a hole, a trench, oranother structure that is substantially filled with air. In someimplementations, an air gap reflection structure 322 may be formedthrough the USG layer 318 and through the ILD layer 320 to a substratelayer 324 of the image sensor 300. In this way, an interface between theair gap reflection structure 322 and the substrate layer 324 is formed.Air has the lowest refractive index of all materials and is the closestto the refractive index of a vacuum. The low refractive index of airrelative to the refractive index of the material of the substrate layer324 lowers the critical angle for a total internal reflection at theinterface between an air gap reflection structure 322 and the materialof the substrate layer 324. Thus, as shown in FIG. 3 , incident lighttraveling through the substrate layer 324 toward the interface betweenan air gap reflection structure 322 and the substrate layer 324 at anangle that is equal to or greater than the critical angle may be totallyreflected off of the interface and upward toward a photodiode 326 of apixel sensor 202. Thus, the lower critical angle increases thelikelihood that a total internal reflection of incident light will occurat the interface between an air gap reflection structure 322 and thesubstrate layer 324, which will cause the incident light to reflect offof the interface and be absorbed by a photodiode of a pixel sensor 202as opposed (or in addition) to the incident light being partiallyrefracted, diffused, or scattered to the ILD layer 320, the USG layer318, and/or the IMD layer 312.

The substrate layer 324 may be referred to as a device substrate onwhich back side processing of the image sensor 300 is performed. Thesubstrate layer 324 may include a silicon layer, a layer formed of amaterial including silicon, a III-V compound semiconductor layer such asgallium arsenide (GaAs) layer, a silicon on insulator (SOI) layer, oranother type of substrate that is capable of generating a charge fromphotons of incident light.

Photodiodes 326 for the pixel sensors 202 in the pixel array 200 may beformed in the substrate layer 324. A photodiode 326 may include a regionof the substrate layer 324 that is doped with a plurality of types ofions to form a p-n junction or a PIN junction (e.g., a junction betweena p-type portion, an intrinsic (or undoped) type portion, and an n-typeportion). For example, the substrate layer 324 may be doped with ann-type dopant to form a first portion (e.g., an n-type portion) of aphotodiode 326 and a p-type dopant to form a second portion (e.g., ap-type portion) of the photodiode 326. A photodiode 326 may beconfigured to absorb photons of incident light. The absorption ofphotons causes a photodiode 326 to accumulate a charge (referred to as aphotocurrent) due to the photoelectric effect. Here, photons bombard thephotodiode 326, which causes emission of electrons of the photodiode326. The emission of electrons causes the formation of electron-holepairs, where the electrons migrate toward the cathode of the photodiode326 and the holes migrate toward the anode, which produces thephotocurrent.

In some implementations, respective pluralities of air gap reflectionstructures 322 may be formed and/or located below and/or under thephotodiodes 326 of one or more pixel sensors 202. For example, aplurality of air gap reflection structures 322 a may be formed throughand/or located in the USG layer 318 and the ILD layer 320 below and/orunder the photodiode 326 of the pixel sensor 202 a, a plurality of airgap reflection structures 322 b may be formed through and/or located inthe USG layer 318 and the ILD layer 320 below and/or under thephotodiode 326 of the pixel sensor 202 b, and so on. In this way, thequantum efficiency of the one or more pixel sensors 202 may be increasedas a result of the reflected photons of incident light by the respectiveplurality of air gap reflection structures 322.

A plurality of deep trench isolation (DTI) structures 328 may beincluded in the substrate layer 324. In particular, DTI structures 328may be formed between each of the photodiodes 326 of the pixel sensors202 such that the photodiodes 326 are surrounded by DTI structures 328.As an example, a DTI structure 328 may be formed between the photodiode326 of the pixel sensor 202 a and the pixel sensor 202 b, a DTIstructure 328 may be formed between the photodiode 326 of the pixelsensor 202 a and an adjacent pixel sensor, a DTI structure 328 may beformed between the photodiode 326 of the pixel sensor 202 b and anadjacent pixel sensor, and so on. The DTI structures 328 may form a gridlayout in which DTI structures 328 extend laterally across the pixelarray 200 and intersect at various locations of the pixel array 200. Insome implementations, the DTI structure 328 may be backside DTI (BDTI)structures formed as a part of back side processing of the image sensor300.

The DTI structures 328 may include trenches (e.g., deep trenches) thatextend downward into the substrate layer 324 along the photodiodes 326.The DTI structures 328 may provide optical isolation between the pixelsensors 202 of the pixel array 200 to reduce the amount of opticalcrosstalk between adjacent pixel sensors 202. In particular, DTIstructures 328 may absorb, refract, and/or reflect incident light, whichmay reduce the amount of incident light that travels through a pixelsensor 202 into an adjacent pixel sensor 202 and is absorbed by theadjacent pixel sensor 202.

One or more high absorption regions 330 may be located in the substratelayer 324, and in and/or above one or more photodiodes 326. Each highabsorption region 330 may be defined by a shallow trench. A plurality ofadjacent high absorption regions 330 may form a periodic or zig-zagstructure in the substrate layer 324 and/or the photodiode(s) 326. Theone or more high absorption regions 330 may be formed in a same side ofthe substrate layer 324 as the DTI structures 328.

A high absorption region 330 may increase the absorption of incidentlight for a pixel sensor 202 (thereby increasing the quantum efficiencyof the pixel sensor 202) by modifying or changing the orientation of therefractive interface between the photodiode 326 of the pixel sensor 202and the substrate layer 324. The angled walls of the high absorptionregion 330 change the orientation of the interface between thephotodiode 326 and the substrate layer 324 by causing the interface tobe diagonal relative to the orientation of a top surface of thesubstrate layer 324. This change in orientation may result in a smallerangle of refraction relative to a flat surface of the top surface of thesubstrate layer 324 for the same angle of incidence of incident light.As a result, the high absorption region 330 is capable of directingwider angles of incident light toward the center of the photodiode 326of the pixel sensor 202 than if no high absorption region 330 wereincluded in the pixel sensor 202.

The top surface of the substrate layer 324, the surfaces of the DTIstructures 328, and the surfaces of the high absorption region(s) 330may be coated with an antireflective coating (ARC) layer 332 to decreasereflection of incident light away from the photodiodes 326 and toincrease transmission of incident light into the substrate layer 324 andthe photodiodes 326. The ARC layer 332 may include a suitable materialfor reducing a reflection of incident light projected toward thephotodiodes 326, such as a nitrogen-containing material or otherexamples.

An oxide layer 334 may be located above the substrate layer 324 andabove and/or on the ARC layer 332. Moreover, the material of the oxidelayer 334 may fill the DTI structures 328 and the high absorptionregion(s) 330. The oxide layer 334 may function as a passivation layerbetween the substrate layer 324 and the upper layers of the pixel array200. In some implementations, the oxide layer 334 includes an oxidematerial such as a silicon oxide (SiO_(x)). In some implementations, asilicon nitride (SiN_(x)), a silicon carbide (SiC_(x)), or a mixturethereof, such as a silicon carbon nitride (SiCN), a silicon oxynitride(SiON), or another dielectric material is used in place of the oxidelayer 334 as a passivation layer.

A metal shielding layer 336 may be located above and/or on the oxidelayer 334 (or portions thereof). The metal shielding layer 336 mayprovide shielding for the components and/or devices formed in the metalshield region 302. The metal shielding layer 336 may be formed of ametal material, such as gold, silver, aluminum, a metal alloy, or asimilar metal. One or more passivation layers may be formed above and/oron the metal shielding layer 336. For example, a BSI oxide layer 338 maybe located above and/or on portions of the oxide layer 334, and aboveand/or on the metal shielding layer 336. As another example, a bufferoxide layer 340 may be located above and/or on the BSI oxide layer 338.In some implementations, the BSI oxide layer 338 and/or the buffer oxidelayer 340 include an oxide material such as a silicon oxide (SiO_(x)).In some implementations, a silicon nitride (SiN_(x)), a silicon carbide(SiC_(x)), or a mixture thereof, such as a silicon carbon nitride(SiCN), a silicon oxynitride (SiON), or another dielectric material isused in place of the BSI oxide layer 338 and/or the buffer oxide layer340 as a passivation layer.

A filter layer 342 may be included above and/or on the buffer oxidelayer 340 for one or more pixel sensors 202 in the pixel array 200. Thefilter layer 342 may include one or more visible light color filterregions configured to filter particular wavelengths or wavelength rangesof visible light (e.g., that permit particular wavelengths or wavelengthranges of visible light to pass through the filter layer 342), one ormore near infrared (NIR) filter regions (e.g., NIR bandpass filterregions) configured to permit wavelengths associated with NIR light topass through the filter layer 342 and to block other wavelengths oflight, one or more NIR cut filter regions configured to block NIR lightfrom passing through the filter layer 342, and/or other types of filterregions. In some implementations, one or more pixel sensors 202 in thepixel array 200 are each configured with a filter region of the filterlayer 342. For example, the pixel sensor 202 a may be configured with afilter region 342 a above the photodiode 326 of the pixel sensor 202 a,the pixel sensor 202 b may be configured with a filter region 342 babove the photodiode 326 of the pixel sensor 202 b, and so on. In someimplementations, filter regions may be omitted from the filter layer 342for one or more pixel sensors 202 in the pixel array 200 to permit allwavelengths of light to pass through the filter layer 342 for the one ormore pixel sensors 202. In these examples, the one or more pixel sensors202 may be configured as white pixel sensors.

A micro-lens layer 344 may be included above and/or on the filter layer342. The micro-lens layer 344 may include a plurality of micro-lenses.In particular, the micro-lens layer 344 may include a respectivemicro-lens for each of the pixel sensors 202 included in the pixel array200. For example, a first micro-lens may be formed to focus incidentlight toward the photodiode 326 of pixel sensor 202 a, a secondmicro-lens may be formed to focus incident light toward the photodiode326 of pixel sensor 202 b, and so on.

As shown in the bonding pad region 304 of the image sensor 300, ashallow trench isolation (STI) structure 346 may be located above and/oron the ILD layer 320 in the bonding pad region 304. The STI structure346 may provide electrical isolation in the bonding pad region 304. Forexample, the STI structure 346 may electrically isolate the pixel array200 and/or the metal shield region 302 from other regions of the imagesensor 300 and/or from other devices formed on the same semiconductordie as the image sensor 300. In some implementations, the buffer oxidelayer 340 may be located above and/or on the STI structure 346 in thebonding pad region 304.

A bonding pad 348 may be located in the bonding pad region 304 above theSTI structure 346, and/or above and/or on the buffer oxide layer 340.The bonding pad 348 may extend through the buffer oxide layer 340,through the STI structure 346, and through the ILD layer 320 to the IMDlayer 312, and may contact one or more metallization layers 314 in theIMD layer 312. The bonding pad 348 may include a conductive material,such as gold, silver, aluminum, copper, aluminum-copper, titanium,tantalum, titanium nitride, tantalum nitride, tungsten, a metal alloy,other metals, or a combination thereof. The bonding pad 348 may provideelectrical connections between the metallization layers 314 of the imagesensor 300 and external devices and/or external packaging.

The number and arrangement of components, structures, and/or layersshown in the image sensor 300 of FIG. 3 are provided as an example. Inpractice, the image sensor 300 may include additional components,structures, and/or layers; fewer components, structures, and/or layers;different components, structures, and/or layers; and/or differentlyarranged components, structures, and/or layers than those shown in FIG.3 .

FIGS. 4A-4S are diagrams of an example implementation 400 describedherein. Example implementation 400 may be an example process for formingthe image sensor 300 including the pixel array 200 (which may include aplurality of pixel sensors 202, such as the pixel sensor 202 a and thepixel sensor 202 b), or a portion thereof. As shown in FIG. 4A, theimage sensor 300 may include the pixel array 200, the metal shieldregion 302, the bonding pad region 304, and the scribe line region 306.Moreover, the image sensor 300 may include the substrate layer 324, theSTI structure 346 formed in the substrate layer 324, the ILD layer 320formed on the substrate layer 324, and the USG layer 318 formed on theILD layer 320.

As shown in FIG. 4B, one or more semiconductor processing tools may forma plurality of openings 402 through the USG layer 318 and at leastpartially in the ILD layer 320. For example, the deposition tool 102 mayform a photoresist layer on the USG layer 318, the exposure tool 104 mayexpose the photoresist layer to a radiation source to pattern thephotoresist layer, the developer tool 106 may develop and removeportions of the photoresist layer to expose the pattern, the etch tool108 may etch a plurality of portions of the USG layer 318 and aplurality of portions of the ILD layer 320 to form the plurality ofopenings 402. In particular, the etch tool 108 may etch through the USGlayer 318 and at least partially into the ILD layer 320 to form theplurality of openings 402. In some implementations, a photoresistremoval tool removes the remaining portions of the photoresist layer(e.g., using a chemical stripper and/or another technique) after theetch tool 108 etches the portions of the USG layer 318 and the portionsof the ILD layer 320.

In some implementations, the one or more semiconductor processing toolsform a plurality of sets of openings 402 through the USG layer 318 andat least partially in the ILD layer 320, where each set of openings 402is formed for a respective pixel sensor 202 of the pixel array 200. Forexample, the one or more semiconductor processing tools may form a setof one or more openings 402 a through the USG layer 318 and at leastpartially in the ILD layer 320 for the pixel sensor 202 a, may formanother set of one or more openings 402 b through the USG layer 318 andat least partially in the ILD layer 320 for the pixel sensor 202 b, andso on. Each set of one or more openings 402 may include one or moreholes, one or more trenches, openings of other shapes, or a combinationthereof. In some implementations, the one or more semiconductorprocessing tools form the size (e.g., depth and/or width), aspect ratio,shape, arrangement, and/or quantity of the openings 402 for a pixelsensor 202 based on the size of the pixel sensor 202 (e.g., largeropenings 402 and/or a greater quantity of openings 402 may be formed forlarger pixel sensors relative to smaller pixel sensors), based on aquantity of air gap reflection structures that are to be formed for thepixel sensor 202, and/or based on other aspects and/or attributes of thepixel sensor 202.

In some implementations, the one or more semiconductor processing toolsform the plurality of openings 402 to satisfy and/or to achieve one ormore performance parameters or thresholds for the pixel array 200(and/or for the image sensor 300). For example, the one or moresemiconductor processing tools may form a particular quantity ofopenings 402 for a pixel sensor 202 to satisfy a quantum efficiencythreshold for the pixel sensor 202, or to achieve a particular quantumefficiency for the pixel sensor 202. As another example, the one or moresemiconductor processing tools may form a particular quantity ofopenings 402 for a pixel sensor 202 to satisfy a strength parameter orto achieve a particular structural integrity for the pixel sensor 202.

As another example, the one or more semiconductor processing tools mayform the plurality of openings 402 for a pixel sensor 202 such that theresulting air gap reflection structures for the pixel sensor 202 have anaspect ratio, between the depth of the air gap reflection structures anda width of the air gap reflection structures, of greater thanapproximately 2. The aspect ratio of greater than approximately 2 mayprovide suitable photon reflection performance for the pixel sensor 202(thereby increasing the quantum efficiency threshold for the pixelsensor 202) while maintaining a sufficient strength for the ILD layer320 and/or one or more other layers of the image sensor 300 (e.g., toreduce and/or minimize the likelihood that the ILD layer 320 and/or theone or more other layers will collapse).

In other examples, the one or more semiconductor processing tools mayform the plurality of openings 402 to a particular shape (or shapes),may form the plurality of openings 402 in a particular arrangement orconfiguration, may form the plurality of openings 402 to a particularsize and/or aspect ratio, and/or may form other aspects and/orattributes of the plurality of openings 402 so as to satisfy and/or toachieve one or more performance parameters or thresholds for the pixelarray 200 (and/or for the image sensor 300).

As shown in FIG. 4C, one or more semiconductor processing tools may formthe IMD layer 312 below and/or over the ILD layer 320, and over and/oron the USG layer 318. For example, the deposition tool 102 may depositthe IMD layer 312 using a CVD technique, a PVD technique, an ALDtechnique, or another type of deposition technique. The formation of theIMD layer 312 may close the openings 402 to form a plurality of air gapreflection structures 322 (e.g., a first set of one or more air gapreflection structures 322 a for the pixel sensor 202 a and a second setof one or more air gap reflection structures 322 b for the pixel sensor202 b, and so on). The deposition tool 102 may deposit the material ofthe IMD layer 312 at a particular deposition rate, or a deposition ratethat satisfies a threshold deposition rate, such that the openings 402are closed or sealed by the IMD layer 312 before the openings 402 can befilled with the material of the IMD layer 312. In this way, air gaps orvoids are formed in the openings 402, resulting in the formation of theair gap reflection structures 322. In some implementations, thedeposition tool 102 deposits the material of the IMD layer 312 at adeposition rate in a range from approximately 2 angstroms per second(A/S) to approximately 300 A/S to cause the openings 402 to be closed orsealed by the IMD layer 312 such that the openings 402 are not filledwith the material of the IMD layer 312.

As further shown in FIG. 4C, one or more semiconductor processing toolsmay form the metallization layers 314 and the contacts 316 in the IMDlayer 312. In some implementations, each metallization layer 314 andeach contact 316 may be formed using a deposition operation or a platingoperation. For example, the plating tool 112 may apply a voltage acrossan anode formed of a plating material and a cathode (e.g., a substrate).The voltage causes a current to oxidize the anode, which causes therelease of plating material ions from the anode. These plating materialions form a plating solution that travels through a plating bath towardthe substrate. The plating solution reaches the substrate and depositsplating material in and/or on the IMD layer 312 to form themetallization layers 314 and the contacts 316.

In some implementations, forming the metallization layers 314 and thecontacts 316 may include a plurality of plating operations. For example,a first portion of the IMD layer 312 may be formed, and themetallization layer 314 a may be formed in the first portion of the IMDlayer 312. A second portion of the IMD layer 312 may be formed, and themetallization layer 314 b (and the contacts 316 connecting themetallization layer 314 a and the metallization layer 314 b) may beformed in the second portion of the IMD layer 312. A third portion ofthe IMD layer 312 may be formed, and the metallization layer 314 c (andthe contacts 316 connecting the metallization layer 314 b and themetallization layer 314 c) may be formed in the third portion of the IMDlayer 312. A fourth portion of the IMD layer 312 may be formed over themetallization layer 314 c to electrically insulate the metallizationlayer 314 c.

As shown in FIG. 4D, one or more semiconductor processing tools may formthe buffer layer 310 over and/or on the IMD layer 312. For example, thedeposition tool 102 may deposit the buffer layer 310 on the IMD layer312. In some implementations, the deposition tool 102 may deposit thebuffer layer 310 using a CVD technique, a PVD technique, an ALDtechnique, or another type of deposition technique. The image sensor 300may be bonded or attached to a carrier substrate using the buffer layer310 so that back side processing may be performed on the image sensor300 to form one or more layers and/or structures on the back side of theimage sensor 300 (e.g., on the side of the substrate layer 324 opposingthe side of the substrate layer 324 on which the ILD layer 320 isformed).

As shown in FIG. 4E, one or more semiconductor processing tools may forma plurality of photodiodes 326 in the substrate layer 324. For example,the implantation tool 114 may dope the portions of the substrate layer324 using an ion implantation technique to form a respective photodiode326 for each of the pixel sensors 202, such as the pixel sensor 202 aand the pixel sensor 202 b. The substrate layer 324 may be doped with aplurality of types of ions to form a p-n junction for each photodiode326. For example, the substrate layer 324 may be doped with an n-typedopant to form a first portion (e.g., an n-type portion) of a photodiode326 and a p-type dopant to form a second portion (e.g., a p-typeportion) of the photodiode 326. In some implementations, anothertechnique is used to form the photodiodes 326 such as diffusion.

The one or more semiconductor processing tools may form the photodiodes326 over and/or above the air gap reflection structures 322. In thisway, the air gap reflection structures 322 are positioned to reflectphotons of incident light toward the photodiodes 326 (e.g., whichreduces refraction, diffusion, and/or scattering of photons to the ILDlayer 320 and/or other layers below the photodiodes 326).

As shown in FIG. 4F, a plurality of DTI structures 328 may be formed inthe substrate layer 324. In particular, a DTI structure 328 may beformed between each of the photodiodes 326 of the pixel sensors 202. Asan example, a DTI structure 328 may be formed between the photodiodes326 of the pixel sensor 202 a and the pixel sensor 202 b, a DTIstructure 328 may be formed between the photodiodes 326 of the pixelsensor 202 a and another adjacent pixel sensor 202, a DTI structure 328may be formed between the photodiodes 326 of the pixel sensor 202 b andanother adjacent pixel sensor 202, and so on.

In some implementations, one or more semiconductor processing tools maybe used to form the DTI structures 328 in the substrate layer 324. Forexample, the deposition tool 102 may form a photoresist layer on thesubstrate layer 324, the exposure tool 104 may expose the photoresistlayer to a radiation source to pattern the photoresist layer, thedeveloper tool 106 may develop and remove portions of the photoresistlayer to expose the pattern, and the etch tool 108 may etch the portionsof substrate layer 324 to form the DTI structures 328 in the substratelayer 324. In some implementations, a photoresist removal tool removesthe remaining portions of the photoresist layer (e.g., using a chemicalstripper and/or another technique) after the etch tool 108 etches thesubstrate layer 324.

As further shown in FIG. 4F, one or more high absorption regions 330 maybe formed in the substrate layer 324 and/or in one or more of thephotodiodes 326. Each high absorption region 330 may be defined by ashallow trench. A plurality of adjacent high absorption regions 330 mayform a periodic or zig-zag structure that is etched or otherwise formedin the substrate layer 324 and/or the photodiode(s) 326. The one or morehigh absorption regions 330 may be formed in a same side of thesubstrate layer 324 as the DTI structures 328, and may be formed usingsimilar techniques and/or semiconductor processes as described above inconnection with forming the DTI structures 328.

In some implementations, each of the pixel sensors 202 included in thepixel array 200 includes one or more high absorption regions 330. Insome implementations, a subset of the pixel sensors 202 include one ormore high absorption regions 330, and the one or more high absorptionregions 330 are omitted from another subset of the pixel sensors 202.

As shown in FIG. 4G, the ARC layer 332 may be formed above and/or on thesubstrate layer 324, may be formed in the DTI structures 328, and may beformed in the high absorption regions 330. In particular, asemiconductor processing tool (e.g., the deposition tool 102) maydeposit the ARC layer 332 using a CVD technique, a PVD technique, an ALDtechnique, or another type of deposition technique. The ARC layer 332may include a suitable material for reducing a reflection of incidentlight projected toward the photodiodes 326. In some implementations, thesemiconductor processing tool may form the ARC layer 332 to a thicknessin a range from approximately 200 angstroms to approximately 1000angstroms.

As shown in FIG. 4H, the one or more DTI structures 328 and the one ormore high absorption regions 330 may each be filled with an oxidematerial. In particular, a semiconductor processing tool (e.g., thedeposition tool 102) may deposit the oxide material such that the oxidelayer 334 is formed in the DTI structures 328, in the high absorptionregions 330, and over the substrate layer 324. The semiconductorprocessing tool may deposit the oxide material using various CVDtechniques and/or ALD techniques, such as PECVD, HDP-CVD, SACVD, orPEALD.

As shown in FIG. 4I, a plurality of openings 404 (or trenches) may beformed through the oxide layer 334 and the ARC layer 332 in the metalshield region 302, and a plurality of openings 406 (or trenches) may beformed through the oxide layer 334 and the ARC layer 332 to thesubstrate layer 324 in the scribe line region 306. The openings 404 and406 may be formed by coating the oxide layer 334 with a photoresist(e.g., using the deposition tool 102), forming a pattern in thephotoresist by exposing the photoresist to a radiation source (e.g.,using the exposure tool 104), removing either the exposed portions orthe non-exposed portions of the photoresist (e.g., using developer tool106), and etching the openings 404 and 406 into the oxide layer 334 andthe ARC layer 332 to the substrate layer 324 (e.g., using the etch tool108) based on the pattern in the photoresist.

As shown in FIG. 4J, the metal shielding layer 336 may be formed overand/or on the oxide layer 334 and in the openings 404 and 406. The metalshielding layer 336 may provide shielding for the components and/ordevices formed in the metal shield region 602 and in the scribe lineregion 306. The metal shielding layer 336 may be formed of a metalmaterial, such as gold, silver, aluminum, a metal alloy, or a similarmetal. In some implementations, a semiconductor processing tool (e.g.,the plating tool 112) may form the metal shielding layer 336 using aplating technique such as electroplating (or electro-chemicaldeposition). In these examples, the semiconductor processing tool mayapply a voltage across an anode formed of a plating material and acathode (e.g., a substrate). The voltage causes a current to oxidize theanode, which causes the release of plating material ions from the anode.These plating material ions form a plating solution that travels througha plating bath toward the image sensor 300. The plating solution reachesthe image sensor 300 and deposits plating material ions onto the oxidelayer 334 and in the openings 404 and 406 to form the metal shieldinglayer 336.

As shown in FIG. 4K, an opening 410 (or a trench) may be formed throughthe metal shielding layer 336 and in a portion of the oxide layer 334 inthe bonding pad region 304, and a plurality of openings 408 (ortrenches) may be formed through the metal shielding layer 336 and in aportion of the oxide layer 334 in the pixel array 200. The openings 408and 410 may be formed by coating the metal shielding layer 336 with aphotoresist (e.g., using the deposition tool 102), forming a pattern inthe photoresist by exposing the photoresist to a radiation source (e.g.,using the exposure tool 104), removing either the exposed portions orthe non-exposed portions of the photoresist (e.g., using developer tool106), and etching the openings 408 and 410 into the metal shieldinglayer and in a portion of the oxide layer 334 (e.g., using the etch tool108) based on the pattern in the photoresist.

As shown in FIG. 4L, the BSI oxide layer 338 may be formed in theopenings 408 and 410, and over the metal shielding layer 336 and theoxide layer 334. In particular, a semiconductor processing tool (e.g.,the deposition tool 102) may deposit an oxide material (e.g., a siliconoxide (SiO_(x)) or another type of oxide) such that the BSI oxide layer338 is formed using various CVD techniques and/or ALD techniques, suchas PECVD, HDP-CVD, SACVD, or PEALD.

As shown in FIG. 4M, the BSI oxide layer 338 may be planarized. Inparticular, a semiconductor processing tool (e.g., the planarizationtool 110) may perform a planarization or polishing process such as CMP.A CMP process may include depositing a slurry (or polishing compound)onto a polishing pad. The carrier substrate including the image sensor300 may be mounted to a carrier, which may rotate the carrier substrateas the carrier substrate is pressed against the polishing pad. Theslurry and polishing pad act as an abrasive that polishes or planarizesthe BSI oxide layer 338 as the carrier substrate is rotated. Thepolishing pad may also be rotated to ensure a continuous supply ofslurry is applied to the polishing pad.

As shown in FIG. 4N, an opening 412 (or trench) may be formed in thebonding pad region 304. In particular the opening 412 may be formedthrough the BSI oxide layer 338, through the metal shielding layer 336,through the oxide layer 334, through the ARC layer 332, and through thesubstrate layer 324 to the STI structure 346. The opening 412 may beformed by coating the BSI oxide layer 338 with a photoresist (e.g.,using the deposition tool 102), forming a pattern in the photoresist byexposing the photoresist to a radiation source (e.g., using the exposuretool 104), removing either the exposed portions or the non-exposedportions of the photoresist (e.g., using developer tool 106), andetching the opening 412 (e.g., using the etch tool 108) based on thepattern in the photoresist.

As shown in FIG. 4O, the buffer oxide layer 340 may be formed over theBSI oxide layer 338 and over the STI structure 346 in the opening 412.In particular, a semiconductor processing tool (e.g., the depositiontool 102) may deposit an oxide material (e.g., a silicon oxide (SiO_(x))or another type of oxide) such that the buffer oxide layer 340 is formedusing various CVD techniques and/or ALD techniques, such as PECVD,HDP-CVD, SACVD, or PEALD.

As shown in FIG. 4P, openings 414 (or vias) may be formed in the opening412 of the bonding pad region 304. In particular, the openings 414 maybe formed through the buffer oxide layer 340, through the STI structure346, through the ILD layer 320, and to a metallization layer 314 (e.g.,the metallization layer 314 a) in the IMD layer 312. The openings 414may be formed by coating the buffer oxide layer 340 with a photoresist(e.g., using the deposition tool 102), forming a pattern in thephotoresist by exposing the photoresist to a radiation source (e.g.,using the exposure tool 104), removing either the exposed portions orthe non-exposed portions of the photoresist (e.g., using developer tool106), and etching the openings 414 (e.g., using the etch tool 108) basedon the pattern in the photoresist.

As shown in FIG. 4Q, the bonding pad 348 may be formed in the openings414. For example, a semiconductor processing tool (e.g., the depositiontool 102 or the plating tool 112) may form a metal layer (e.g., analuminum layer, a gold layer, a silver layer, a metal alloy layer, oranother type of metal layer) on the buffer oxide layer 340, on the STIstructure 346, and in the openings 414. Portions of the metal layer maybe removed by coating the metal layer with a photoresist (e.g., usingthe deposition tool 102), forming a pattern in the photoresist byexposing the photoresist to a radiation source (e.g., using the exposuretool 104), removing either the exposed portions or the non-exposedportions of the photoresist (e.g., using developer tool 106), andetching the portions (e.g., using the etch tool 108) based on thepattern in the photoresist to form the bonding pad 348.

As shown in FIG. 4R, the filter layer 342 is formed for the pixelsensors in the pixel array 200. The filter layer 342 may be formed overand/or on the buffer oxide layer 340. In some implementations, asemiconductor processing tool (e.g., the deposition tool 102) maydeposit the filter layer 342 using a CVD technique, a PVD technique, anALD technique, or another type of deposition technique. As shown in FIG.4S, a micro-lens layer 344 including a plurality of micro-lenses isformed over and/or on the filter layer 342. The micro-lens layer 344 mayinclude a respective micro-lens for each of the pixel sensors 202included in the pixel array 200.

As indicated above, FIGS. 4A-4S are provided as an example. Otherexamples may differ from what is described with regard to FIGS. 4A-4S.

FIG. 5 is a diagram of an example image sensor 500 (or a portionthereof) described herein. The image sensor 500 includes another exampleof an image sensor that includes one or more air gap reflectionstructures under the photodiodes of one or more pixel sensors of theimage sensor to reflect photons that would otherwise partially refractor scatter through a bottom surface of the photodiodes. As shown in FIG.5 , the image sensor 500 may include similar regions as the image sensor300 of FIG. 3 , such as the pixel array 200, a metal shield region 502,a bonding pad region 504, and a scribe line region 506. The pixel array200 may include the pixel sensors 202 of the image sensor 500, such aspixel sensor 202 a and pixel sensor 202 b. In some implementations, theimage sensor 300 includes a greater quantity of pixel sensors 202 orfewer pixel sensors 202 than the quantity of pixel sensors illustratedin FIG. 5 .

As further shown in FIG. 5 , the image sensor 500 may include similarlayers and structures as the image sensor 300 of FIG. 3 , such as abuffer layer 510, an ILD layer 520 above and/or on the buffer layer 510,a plurality of metallization layers 514 and a plurality of contacts 516in the IMD layer 512, a USG layer 518 above and/or on the IMD layer 512,an ILD layer 520 above and/or on the IMD layer 512, a plurality of airgap reflection structures 522 (e.g., one or more air gap reflectionstructures 522 a included in pixel sensor 202 a, one or more air gapreflection structures 522 b included in the pixel sensor 202 b, and soon), and a substrate layer 524 above and/or on the ILD layer 520.Moreover, the image sensor 500 may include photodiodes 526 and DTIstructures 528 in the substrate layer 524 for each of the pixel sensors202, one or more high absorption regions 330 in the substrate layer 324and in one or more photodiodes 526, an ARC layer 532 above and/or on thesubstrate layer 524, an oxide layer 534 above and/or on the ARC layer532, a metal shielding layer 536 above and/or on the oxide layer 534, aBSI oxide layer 538 above and/or on portions of the oxide layer 534 andthe metal shielding layer 536, a buffer oxide layer 540 above and/or onthe BSI oxide layer 538, a filter layer 542 above and/or on the bufferoxide layer 540 (e.g., including filter 542 a, filter 542 b, and/orother filters), and micro-lens layer 544 above and/or on the filterlayer 542. In addition, the image sensor 500 may include an STIstructure 546 may be located above and/or on the ILD layer 520 in thebonding pad region 504, and a bonding pad 548 in the bonding pad region504 above the STI structure 546 and above and/or on the buffer oxidelayer 540.

As further shown in FIG. 5 , the IMD layer 512 of the image sensor 500may include a plurality of layers or portions that may be formed over aplurality of deposition operations performed by the deposition tool 102and/or another semiconductor processing tool. The plurality of layersmay include a first layer 512 a formed over and/or on the ILD layer 520,a second layer 512 b formed over and/or the first layer 512 a, a thirdlayer 512 c formed over and/or on the second layer 512 b, a fourth layer512 d formed over and/or on the third layer 512 c, and so on.

Moreover, the metallization layers 514 and the contacts 516 may beformed as part of a deposition operation to form a layer of the IMDlayer 512 or in between deposition operations. For example, ametallization layer 514 a and/or one or more contacts 516 may be formed(e.g., by deposition tool 102, plating tool 112, and/or anothersemiconductor processing tool) as part of the deposition operation toform the first layer 512 a and/or in between the deposition operation toform the first layer 512 a and the deposition operation to form thesecond layer 512 b. As another example, a metallization layer 514 b andone or more contacts 516 may be formed (e.g., by deposition tool 102,plating tool 112, and/or another semiconductor processing tool) as partof the deposition operation to form the second layer 512 b and/or inbetween the deposition operation to form the second layer 512 b and thedeposition operation to form the third layer 512 c. As another example,a metallization layer 514 c and one or more contacts 516 may be formed(e.g., by deposition tool 102, plating tool 112, and/or anothersemiconductor processing tool) as part of the deposition operation toform the third layer 512 c and/or in between the deposition operation toform the third layer 512 c and the deposition operation to form thefourth layer 512 d. As another example, a metallization layer 514 d andone or more contacts 516 may be formed (e.g., by deposition tool 102,plating tool 112, and/or another semiconductor processing tool) as partof the deposition operation to form the fourth layer 512 d and/or inbetween the deposition operation to form the fourth layer 512 d and thedeposition operation to form the buffer layer 510.

As further shown in FIG. 5 , the air gap reflection structures 522 maybe formed in the IMD layer 512 (as opposed to the ILD layer 520). Asshown in the example in FIG. 5 , the air gap reflection structures 522may be formed and included in the second layer 512 b of the IMD layer512. In some implementations, the air gap reflection structures 522 areformed and included in other layers of the IMD layer 512, such as thefirst layer 512 a. In some implementations, the air gap reflectionstructures 522 are formed and included in a plurality of layers of theIMD layer 512.

The image sensor 500 may be formed using similar techniques and/oroperations described above in connection with FIGS. 4A-4S. In someimplementations, the air gap reflection structures 522 are formed in theIMD layer 512 by depositing (e.g., using the deposition tool 102) thefirst layer 512 a over and/or on the ILD layer 520, depositing (e.g.,using the deposition tool 102) the second layer 512 b over and/or on thefirst layer 512 a, forming (e.g., using the deposition tool 102, theexposure tool 104, the developer tool 106, the etch tool 108, and/oranother semiconductor processing tool) one or more openings at leastpartially in the second layer 512 b, and depositing (e.g., using thedeposition tool 102) the third layer 512 c over and/or on the secondlayer 512 b at a deposition rate that causes the opening(s) to be closedor sealed before the material of the third layer 512 c fills theopening(s).

The number and arrangement of components, structures, and/or layersshown in the image sensor 500 of FIG. 5 are provided as an example. Inpractice, the image sensor 500 may include additional components,structures, and/or layers; fewer components, structures, and/or layers;different components, structures, and/or layers; and/or differentlyarranged components, structures, and/or layers than those shown in FIG.5 .

FIG. 6 is a diagram of an example image sensor 600 (or a portionthereof) described herein. The image sensor 600 includes another exampleof an image sensor that includes one or more air gap reflectionstructures under the photodiodes of one or more pixel sensors of theimage sensor to reflect photons that would otherwise partially refractor scatter through a bottom surface of the photodiodes. As shown in FIG.6 , the image sensor 600 may include similar regions as the image sensor300 of FIG. 3 , such as the pixel array 200, a metal shield region 602,a bonding pad region 604, and a scribe line region 606. The pixel array200 may include the pixel sensors 202 of the image sensor 600, such aspixel sensor 202 a and pixel sensor 202 b. In some implementations, theimage sensor 300 includes a greater quantity of pixel sensors 202 orfewer pixel sensors 202 than the quantity of pixel sensors illustratedin FIG. 6 .

As further shown in FIG. 6 , the image sensor 600 may include similarlayers and structures as the image sensor 300 of FIG. 3 , such as abuffer layer 610, an ILD layer 620 above and/or on the buffer layer 610,a plurality of metallization layers 614 and a plurality of contacts 616in the IMD layer 612, a USG layer 618 above and/or on the IMD layer 612,an ILD layer 620 above and/or on the IMD layer 612, a plurality of airgap reflection structures 622 (e.g., one or more air gap reflectionstructures 622 a included in pixel sensor 202 a, one or more air gapreflection structures 622 b included in the pixel sensor 202 b, and soon), and a substrate layer 624 above and/or on the ILD layer 620.Moreover, the image sensor 600 may include photodiodes 626 and DTIstructures 628 in the substrate layer 624 for each of the pixel sensors202, one or more high absorption regions 330 in the substrate layer 324and in one or more photodiodes 626, an ARC layer 632 above and/or on thesubstrate layer 624, an oxide layer 634 above and/or on the ARC layer632, a metal shielding layer 636 above and/or on the oxide layer 634, aBSI oxide layer 638 above and/or on portions of the oxide layer 634 andthe metal shielding layer 636, a buffer oxide layer 640 above and/or onthe BSI oxide layer 638, a filter layer 642 above and/or on the bufferoxide layer 640 (e.g., including filter 642 a, filter 642 b, and/orother filters), and micro-lens layer 644 above and/or on the filterlayer 642. In addition, the image sensor 600 may include an STIstructure 646 may be located above and/or on the ILD layer 620 in thebonding pad region 604, and a bonding pad 648 in the bonding pad region604 above the STI structure 646 and above and/or on the buffer oxidelayer 640.

As further shown in FIG. 6 , the IMD layer 612 of the image sensor 600may include a plurality of layers or portions that may be formed over aplurality of deposition operations performed by the deposition tool 102and/or another semiconductor processing tool. The plurality of layersmay include a first layer 612 a formed over and/or on the ILD layer 620,a second layer 612 b formed over and/or the first layer 612 a, a thirdlayer 612 c formed over and/or on the second layer 612 b, a fourth layer612 d formed over and/or on the third layer 612 c, and so on.

Moreover, the metallization layers 614 and the contacts 616 may beformed as part of a deposition operation to form a layer of the IMDlayer 612 or in between deposition operations. For example, ametallization layer 614 a and/or one or more contacts 616 may be formed(e.g., by deposition tool 102, plating tool 112, and/or anothersemiconductor processing tool) as part of the deposition operation toform the first layer 612 a and/or in between the deposition operation toform the first layer 612 a and the deposition operation to form thesecond layer 612 b. As another example, a metallization layer 614 b andone or more contacts 616 may be formed (e.g., by deposition tool 102,plating tool 112, and/or another semiconductor processing tool) as partof the deposition operation to form the second layer 612 b and/or inbetween the deposition operation to form the second layer 612 b and thedeposition operation to form the third layer 612 c. As another example,a metallization layer 614 c and one or more contacts 616 may be formed(e.g., by deposition tool 102, plating tool 112, and/or anothersemiconductor processing tool) as part of the deposition operation toform the third layer 612 c and/or in between the deposition operation toform the third layer 612 c and the deposition operation to form thefourth layer 612 d. As another example, a metallization layer 614 d andone or more contacts 616 may be formed (e.g., by deposition tool 102,plating tool 112, and/or another semiconductor processing tool) as partof the deposition operation to form the fourth layer 612 d and/or inbetween the deposition operation to form the fourth layer 612 d and thedeposition operation to form the buffer layer 610.

As further shown in FIG. 6 , a first subset of the air gap reflectionstructures 622 (e.g., the air gap reflection structure(s) 622 a) may beformed in the ILD layer 620, and a second subset of the air gapreflection structures 622 (e.g., the air gap reflection structure(s) 622b) may be formed in the IMD layer 612 (e.g., in one or more layers ofthe IMD layer 612). In this way, a first subset of pixel sensors 202 ofthe image sensor 600 may include air gap reflection structure(s) in theILD layer 620, and a second subset of pixel sensors 202 of the imagesensor 600 may include air gap reflection structure(s) in the IMD layer612. In some implementations, air gap reflection structures 622 may beincluded in the IMD layer 612 or the ILD layer 620 for a pixel sensor202 based on various factors, such as a target quantum efficiency, theavailability of space in the IMD layer 612 or the ILD layer 620 for theair gap reflection structures 622, and/or other factors.

The number and arrangement of components, structures, and/or layersshown in the image sensor 600 of FIG. 6 are provided as an example. Inpractice, the image sensor 600 may include additional components,structures, and/or layers; fewer components, structures, and/or layers;different components, structures, and/or layers; and/or differentlyarranged components, structures, and/or layers than those shown in FIG.6 .

FIG. 7 is a diagram of an example image sensor 700 (or a portionthereof) described herein. The image sensor 700 includes another exampleof an image sensor that includes one or more air gap reflectionstructures under the photodiodes of one or more pixel sensors of theimage sensor to reflect photons that would otherwise partially refractor scatter through a bottom surface of the photodiodes. As shown in FIG.7 , the image sensor 700 may include similar regions as the image sensor300 of FIG. 3 , such as the pixel array 200, a metal shield region 702,a bonding pad region 704, and a scribe line region 706. The pixel array200 may include the pixel sensors 202 of the image sensor 700, such aspixel sensor 202 a and pixel sensor 202 b. In some implementations, theimage sensor 300 includes a greater quantity of pixel sensors 202 orfewer pixel sensors 202 than the quantity of pixel sensors illustratedin FIG. 7 .

As further shown in FIG. 7 , the image sensor 700 may include similarlayers and structures as the image sensor 300 of FIG. 3 , such as abuffer layer 710, an IMD layer 712 above and/or on the buffer layer 710,a plurality of metallization layers 714 and a plurality of contacts 716in the IMD layer 712, a USG layer 718 above and/or on the IMD layer 712,an ILD layer 720 above and/or on the IMD layer 712, a plurality of airgap reflection structures 722, and a substrate layer 724 above and/or onthe ILD layer 720. Moreover, the image sensor 700 may includephotodiodes 726 and DTI structures 728 in the substrate layer 724 foreach of the pixel sensors 202, one or more high absorption regions 330in the substrate layer 324 and in one or more photodiodes 726, an ARClayer 732 above and/or on the substrate layer 724, an oxide layer 734above and/or on the ARC layer 732, a metal shielding layer 736 aboveand/or on the oxide layer 734, a BSI oxide layer 738 above and/or onportions of the oxide layer 734 and the metal shielding layer 736, abuffer oxide layer 740 above and/or on the BSI oxide layer 738, a filterlayer 742 above and/or on the buffer oxide layer 740 (e.g., includingfilter 742 a, filter 742 b, and/or other filters), and micro-lens layer744 above and/or on the filter layer 742. In addition, the image sensor700 may include an STI structure 746 may be located above and/or on theILD layer 720 in the bonding pad region 704, and a bonding pad 748 inthe bonding pad region 704 above the STI structure 746 and above and/oron the buffer oxide layer 740.

As further shown in FIG. 7 , the IMD layer 712 of the image sensor 700may include a plurality of layers or portions that may be formed over aplurality of deposition operations performed by the deposition tool 102and/or another semiconductor processing tool. The plurality of layersmay include a first layer 712 a formed over and/or on the ILD layer 720,a second layer 712 b formed over and/or the first layer 712 a, a thirdlayer 712 c formed over and/or on the second layer 712 b, a fourth layer712 d formed over and/or on the third layer 712 c, and so on.

Moreover, the metallization layers 714 and the contacts 716 may beformed as part of a deposition operation to form a layer of the IMDlayer 712 or in between deposition operations. For example, ametallization layer 714 a and/or one or more contacts 716 may be formed(e.g., by deposition tool 102, plating tool 112, and/or anothersemiconductor processing tool) as part of the deposition operation toform the first layer 712 a and/or in between the deposition operation toform the first layer 712 a and the deposition operation to form thesecond layer 712 b. As another example, a metallization layer 714 b andone or more contacts 716 may be formed (e.g., by deposition tool 102,plating tool 112, and/or another semiconductor processing tool) as partof the deposition operation to form the second layer 712 b and/or inbetween the deposition operation to form the second layer 712 b and thedeposition operation to form the third layer 712 c. As another example,a metallization layer 714 c and one or more contacts 716 may be formed(e.g., by deposition tool 102, plating tool 112, and/or anoth12ersemiconductor processing tool) as part of the deposition operation toform the third layer 712 c and/or in between the deposition operation toform the third layer 712 c and the deposition operation to form thefourth layer 712 d. As another example, a metallization layer 714 d andone or more contacts 716 may be formed (e.g., by deposition tool 102,plating tool 112, and/or another semiconductor processing tool) as partof the deposition operation to form the fourth layer 712 d and/or inbetween the deposition operation to form the fourth layer 712 d and thedeposition operation to form the buffer layer 710.

As further shown in FIG. 7 , one or more of the pixel sensors 202included in the image sensor 700 may include a plurality of sets of airgap reflection structures 722. For example, the pixel sensor 202 a mayinclude a first set of one or more air gap reflection structures 722 ain the ILD layer 720 below the photodiode 726 of the pixel sensor 202 a,and a second set of one or more air gap reflection structures 722 bincluded the IMD layer 712 below the first set of one or more air gapreflection structures 722 a. As another example, the pixel sensor 202 bmay include a first set of one or more air gap reflection structures 722c in the ILD layer 720 below the photodiode 726 of the pixel sensor 202b, and a second set of one or more air gap reflection structures 722 dincluded the IMD layer 712 below the first set of one or more air gapreflection structures 722 c. The first set of one or more air gapreflection structures 722 a and the first set of one or more air gapreflection structures 722 c may be adjacent in the ILD layer 720. Thesecond set of one or more air gap reflection structures 722 b and thesecond set of one or more air gap reflection structures 722 b may beadjacent in the IMD layer 712.

Including a set of air gap reflection structures 722 in the ILD layer720 for a pixel sensor 202, and another set of air gap reflectionstructures 722 in the IMD layer 712 for the pixel sensor 202 may furtherincrease the quantum efficiency of the pixel sensor 202. In this way,photons of incident light that may refract, diffuse, and/or scatterthrough the photodiode 726 of the pixel sensor 202 that are notreflected by the air gap reflection structures 722 in the ILD layer 720may still be reflected upward toward the photodiode 726 by the air gapreflection structures 722 in the IMD layer 712, which increases theabsorption of incident light for the pixel sensor 202.

The number and arrangement of components, structures, and/or layersshown in the image sensor 700 of FIG. 7 are provided as an example. Inpractice, the image sensor 700 may include additional components,structures, and/or layers; fewer components, structures, and/or layers;different components, structures, and/or layers; and/or differentlyarranged components, structures, and/or layers than those shown in FIG.7 .

FIG. 8 is a diagram of example air gap reflection structureconfigurations described herein. In particular, FIG. 8 illustratestop-down views of example air gap reflection structure configurationsfor a pixel sensor 202 that may be included in the image sensor 300, theimage sensor 500, the image sensor 600, the image sensor 700, and/or oneor more other image sensors. As shown in FIG. 8 , an example air gapreflection structure configuration 810 may include a plurality of holes820 that extend into an ILD layer of an image sensor or into an IMDlayer of the image sensor. The holes 820 may be arranged in asubstantially symmetrical grid layout below the photodiode 326 of thepixel sensor 202, and may be configured to reflect photons of lightupward toward the photodiode 326. In some implementations, a symmetricalgrid layout of holes 820 may include a greater quantity of holes 820 orfewer holes 820. In some implementations, the holes 820 may be arrangedin another symmetrical configuration, such as a reflection-symmetricalconfiguration, a rotational-symmetrical configuration, or atranslational-symmetrical configuration, among other examples.

As further shown in FIG. 8 , another example air gap reflectionstructure configuration 830 may include a plurality of holes 820 in anon-symmetrical (asymmetrical) arrangement. The holes 820 may bearranged in a repeating pattern (e.g., a pattern that alternates betweena row of 4 holes 820 and a row of 5 holes 820), a non-standard layout,or another type of layout.

As further shown in FIG. 8 , another example air gap reflectionstructure configuration 840 may include a plurality of trenches 850. Thetrenches 850 may be arranged in rows below the photodiode 326 of thepixel sensor 202. The trenches 850 may be evenly spaced, may benon-evenly spaced, or a combination thereof. The trenches 850 may be thesame length, may be different lengths, or a combination thereof.

As further shown in FIG. 8 , another example air gap reflectionstructure configuration 860 may include a first plurality of trenches850 and a second plurality of trenches 870. The first plurality oftrenches 850 may be arranged in rows, and the second plurality oftrenches 870 may be arranged in rows and may extend in a direction thatis substantially perpendicular to the plurality of trenches 850. In someimplementations, the first plurality of trenches 850 may extenddiagonally at an angle relative to the second plurality of trenches 870(e.g., such that the first plurality of trenches 850 and the secondplurality of trenches 870 are not diagonal).

As indicated above, FIG. 8 is provided as one or more examples. Otherexamples may differ from what is described with regard to FIG. 8 . Forexample, other examples of air gap reflection structure configurationsfor a pixel sensor 202 may include a greater quantity of holes, fewerholes, differently arranged holes, a greater quantity of trenches, fewertrenches, differently arranged trenches, combinations of holes andtrenches (and/or other shapes of air gap reflection structures), or acombination thereof. In some implementations, a particular air gapreflection structure configuration may be selected based on the size ofa pixel sensor 202, based on one or more performance parameters for thepixel sensor 202, and/or based on other parameters.

FIG. 9 is a diagram of example components of a device 900. In someimplementations, one or more of the semiconductor processing tools102-116 may include one or more devices 900 and/or one or morecomponents of device 900. As shown in FIG. 9 , device 900 may include abus 910, a processor 920, a memory 930, a storage component 940, aninput component 950, an output component 960, and a communicationcomponent 970.

Bus 910 includes a component that enables wired and/or wirelesscommunication among the components of device 900. Processor 920 includesa central processing unit, a graphics processing unit, a microprocessor,a controller, a microcontroller, a digital signal processor, afield-programmable gate array, an application-specific integratedcircuit, and/or another type of processing component. Processor 920 isimplemented in hardware, firmware, or a combination of hardware andsoftware. In some implementations, processor 920 includes one or moreprocessors capable of being programmed to perform a function. Memory 930includes a random access memory, a read only memory, and/or another typeof memory (e.g., a flash memory, a magnetic memory, and/or an opticalmemory).

Storage component 940 stores information and/or software related to theoperation of device 900. For example, storage component 940 may includea hard disk drive, a magnetic disk drive, an optical disk drive, a solidstate disk drive, a compact disc, a digital versatile disc, and/oranother type of non-transitory computer-readable medium. Input component950 enables device 900 to receive input, such as user input and/orsensed inputs. For example, input component 950 may include a touchscreen, a keyboard, a keypad, a mouse, a button, a microphone, a switch,a sensor, a global positioning system component, an accelerometer, agyroscope, and/or an actuator. Output component 960 enables device 900to provide output, such as via a display, a speaker, and/or one or morelight-emitting diodes. Communication component 970 enables device 900 tocommunicate with other devices, such as via a wired connection and/or awireless connection. For example, communication component 970 mayinclude a receiver, a transmitter, a transceiver, a modem, a networkinterface card, and/or an antenna.

Device 900 may perform one or more processes described herein. Forexample, a non-transitory computer-readable medium (e.g., memory 930and/or storage component 940) may store a set of instructions (e.g., oneor more instructions, code, software code, and/or program code) forexecution by processor 920. Processor 920 may execute the set ofinstructions to perform one or more processes described herein. In someimplementations, execution of the set of instructions, by one or moreprocessors 920, causes the one or more processors 920 and/or the device900 to perform one or more processes described herein. In someimplementations, hardwired circuitry may be used instead of or incombination with the instructions to perform one or more processesdescribed herein. Thus, implementations described herein are not limitedto any specific combination of hardware circuitry and software.

The number and arrangement of components shown in FIG. 9 are provided asan example. Device 900 may include additional components, fewercomponents, different components, or differently arranged componentsthan those shown in FIG. 9 . Additionally, or alternatively, a set ofcomponents (e.g., one or more components) of device 900 may perform oneor more functions described as being performed by another set ofcomponents of device 900.

FIG. 10 is a flowchart of an example process 1000 associated withforming an image sensor. In some implementations, one or more processblocks of FIG. 10 may be performed by one or more semiconductorprocessing tools (e.g., one or more of the semiconductor processingtools 102-116). Additionally, or alternatively, one or more processblocks of FIG. 10 may be performed by one or more components of device900, such as processor 920, memory 930, storage component 940, inputcomponent 950, output component 960, and/or communication component 970.

As shown in FIG. 10 , process 1000 may include forming, for a pixelsensor 202 of a pixel array included in an image sensor, a plurality ofopenings through a USG layer of the image sensor and in an ILD layer ofthe image sensor (block 1010). For example, one or more semiconductorprocessing tools (e.g., the deposition tool 102, the exposure tool 104,the developer tool 106, the etch tool 108, and/or another semiconductorprocessing tool) may form, for a pixel sensor (202) of a pixel array(200) included in an image sensor (300, 500, 600, 700), a plurality ofopenings (402 a, 402 b) through an USG layer (318, 518, 618, 718) of theimage sensor and in an ILD layer (320, 520, 620, 720) of the imagesensor, as described above.

As further shown in FIG. 10 , process 1000 may include forming an IMDlayer on the USG layer, where the IMD layer closes the plurality ofopenings to form a plurality of air gap reflection structures of thepixel sensor (block 1020). For example, a semiconductor processing tool(e.g., the deposition tool 102) may form an IMD layer (312, 512, 612,712) on the USG layer (318, 518, 618, 718), as described above. In someimplementations, the IMD layer (312, 512, 612, 712) closes the pluralityof openings (402 a, 402 b) to form a plurality of air gap reflectionstructures (322, 522, 622, 722) of the pixel sensor (202).

As further shown in FIG. 10 , process 1000 may include forming aphotodiode in a silicon layer above the ILD layer, where the photodiodeis formed over the plurality of air gap reflection structures (block1030). For example, a semiconductor processing tool (e.g., the ionimplantation tool 114) may form a photodiode (326, 526, 626, 726) in asilicon layer (324, 524, 624, 724) above the ILD layer (320, 520, 620,720), as described above. In some implementations, the photodiode (326,526, 626, 726) is formed over the plurality of air gap reflectionstructures (322, 522, 622, 722).

Process 1000 may include additional implementations, such as any singleimplementation or any combination of implementations described belowand/or in connection with one or more other processes describedelsewhere herein.

In a first implementation, forming the plurality of openings (402 a, 402b) includes forming a quantity of the plurality of openings (402 a, 402b) based on a size of the pixel sensor (202). In a secondimplementation, alone or in combination with the first implementation,forming the plurality of openings (402 a, 402 b) includes forming eachof the plurality of openings (402 a, 402 b) to at least one of aparticular depth or a particular width based on at least one of a sizeof the pixel sensor (202) or a quantity of the air gap reflectionstructures (322, 522, 622, 722) to be formed for the pixel sensor (202).

In a third implementation, alone or in combination with one or more ofthe first and second implementations, the plurality of air gapreflection structures (322, 522, 622, 722) include a first plurality ofair gap reflection structures (722 a), and process 1000 includes forming(e.g., using the deposition tool 102, the exposure tool 104, thedeveloper tool 106, the etch tool 108, and/or another semiconductorprocessing tool) a second plurality of air gap reflection structures(722 c) in the ILD layer (720) for a second pixel sensor (202 b) of thepixel array, wherein the second plurality of air gap reflectionstructures (722 c) are adjacent to the first plurality of air gapreflection structures (722 a), forming (e.g., using the deposition tool102, the exposure tool 104, the developer tool 106, the etch tool 108,and/or another semiconductor processing tool) a third plurality of airgap reflection structures (722 b) in the IMD layer (712), wherein thethird plurality of air gap reflection structures (722 b) are under thefirst plurality of air gap reflection structures (722 a), and forming afourth plurality of air gap reflection structures (722 d) in the IMDlayer (712), wherein the fourth plurality of air gap reflectionstructures (722 d) are under the second plurality of air gap reflectionstructures (722 c).

In a fourth implementation, alone or in combination with one or more ofthe first through third implementations, process 1000 includes forming(e.g., using the deposition tool 102, the exposure tool 104, thedeveloper tool 106, the etch tool 108, and/or another semiconductorprocessing tool) a first DTI structure (328, 528, 628, 728) on a firstside of the photodiode (326, 526, 626, 726) in the silicon layer (324,524, 624, 724), and forming (e.g., using the deposition tool 102, theexposure tool 104, the developer tool 106, the etch tool 108, and/oranother semiconductor processing tool) a second DTI structure on asecond side (328, 528, 628, 728) of the photodiode (326, 526, 626, 726)in the silicon layer (324, 524, 624, 724). In a fifth implementation,alone or in combination with one or more of the first through fourthimplementations, process 1000 includes forming (e.g., using thedeposition tool 102, the exposure tool 104, the developer tool 106, theetch tool 108, and/or another semiconductor processing tool) a pluralityof high absorption regions (330, 530, 630, 730) in the photodiode (326,526, 626, 726) and in the silicon layer (324, 524, 624, 724).

Although FIG. 10 shows example blocks of process 1000, in someimplementations, process 1000 may include additional blocks, fewerblocks, different blocks, or differently arranged blocks than thosedepicted in FIG. 10 . Additionally, or alternatively, two or more of theblocks of process 1000 may be performed in parallel.

In this way, a pixel array may include air gap reflection structuresunder a photodiode of a pixel sensor to reflect photons that wouldotherwise partially refract or scatter through a bottom surface of aphotodiode. The air gap reflection structures may reflect photons upwardtoward the photodiode so that the photons may be absorbed by thephotodiode. This may increase the quantity of photons absorbed by thephotodiode, which may increase the quantum efficiency of the pixelsensor and the pixel array.

As described in greater detail above, some implementations describedherein provide a pixel array. The pixel array includes a plurality ofpixel sensors. A pixel sensor of the plurality of pixel sensors includesa photodiode in a silicon layer of the pixel array. The pixel sensorincludes one or more air gap reflection structures below the photodiodeand in an ILD layer that is below the silicon layer.

As described in greater detail above, some implementations describedherein provide a pixel array. The pixel array includes a first pixelsensor including a first photodiode in a silicon layer of the pixelarray. The first pixel sensor includes a first plurality of air gapreflection structures under the first photodiode and in an ILD layerthat is below the silicon layer or an IMD layer that is below the ILDlayer. The pixel array includes a second pixel sensor that includes asecond photodiode in the silicon layer. The second pixel sensor includesa second plurality of air gap reflection structures under the secondphotodiode and in the ILD layer or the IMD layer.

As described in greater detail above, some implementations describedherein provide a method. The method includes forming, for a pixel sensorof a pixel array included in an image sensor, a plurality of openingsthrough an USG layer of the image sensor and in an ILD layer of theimage sensor. The method includes forming an IMD layer on the USG layer,where the IMD layer closes the plurality of openings to form a pluralityof air gap reflection structures. of the pixel sensor. The methodincludes forming a photodiode in a silicon layer above the ILD layer,where the photodiode is formed over the plurality of air gap reflectionstructures.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A pixel array, comprising: a plurality of pixelsensors, a pixel sensor of the plurality of pixel sensors comprising: aphotodiode in a silicon layer of the pixel array; one or more first airgap reflection structures below the photodiode and in an interlayerdielectric (ILD) layer that is below the silicon layer; and one or moresecond air gap reflection structures under the one or more first air gapreflection structures.
 2. The pixel array of claim 1, wherein the one ormore first air gap reflection structures are configured to reflectincident light upward toward the photodiode.
 3. The pixel array of claim1, wherein an aspect ratio, between a depth of an air gap reflectionstructure of the one or more first air gap reflection structures and awidth of the air gap reflection structure, is greater than approximately2.
 4. The pixel array of claim 1, wherein the one or more first air gapreflection structures include a plurality of holes that are arranged inan asymmetric configuration.
 5. The pixel array of claim 1, wherein theone or more first air gap reflection structures include a plurality ofholes that are arranged in a substantially symmetrical grid.
 6. Thepixel array of claim 1, wherein the one or more first air gap reflectionstructures include a plurality of trenches.
 7. The pixel array of claim1, wherein the one or more first air gap reflection structures include:a first plurality of trenches; and a second plurality of trenches thatare perpendicular to and intersect the first plurality of trenches.
 8. Apixel array, comprising: a first pixel sensor comprising: a firstphotodiode in a silicon layer of the pixel array; and a first pluralityof air gap reflection structures under the first photodiode and in: aninterlayer dielectric (ILD) layer that is below the silicon layer, or aninter-metal dielectric (IMD) layer that is below the ILD layer; and asecond pixel sensor comprising: a second photodiode in the siliconlayer; a second plurality of air gap reflection structures under thesecond photodiode and in: the ILD layer, or the IMD layer; and a thirdplurality of air gap reflection structures under the second plurality ofair gap reflection structures.
 9. The pixel array of claim 8, whereinthe first plurality of air gap reflection structures and the secondplurality of air gap reflection structures are in the ILD layer.
 10. Thepixel array of claim 9, further comprising: a fourth plurality of airgap reflection structures in the IMD layer and under the first pluralityof air gap reflection structures.
 11. The pixel array of claim 10,wherein the third plurality of air gap reflection structures are in theIMD layer.
 12. The pixel array of claim 8, wherein the first pluralityof air gap reflection structures and the second plurality of air gapreflection structures are in the ILD layer.
 13. The pixel array of claim12, wherein the third plurality air gap reflection structures areadjacent to a metallization layer in the IMD layer.
 14. The pixel arrayof claim 8, wherein the second plurality of air gap reflectionstructures are in the ILD layer; and wherein the third plurality of airgap reflection structures are in the IMD layer.
 15. A pixel array,comprising: a first pixel sensor comprising: a first photodiode in asilicon layer of the pixel array; and a first plurality of air gapreflection structures under the first photodiode and in an interlayerdielectric (ILD) layer; and a second pixel sensor comprising: a secondphotodiode in the silicon layer; and a second plurality of air gapreflection structures under the second photodiode and in an inter-metaldielectric (IMD) layer.
 16. The pixel array of claim 15, wherein the IMDlayer is below the ILD layer.
 17. The pixel array of claim 15, whereinthe first pixel sensor further comprises: a third plurality of air gapreflection structures in the IMD layer.
 18. The pixel array of claim 15,wherein the second pixel sensor further comprises: a third plurality ofair gap reflection structures in the ILD layer.
 19. The pixel array ofclaim 15, wherein the IMD layer includes a plurality of layers; andwherein the second plurality of air gap reflection structures are in anintermediate layer of the plurality of layers.
 20. The pixel array ofclaim 15, wherein the IMD layer includes a metallization layer.